1. Field of the Invention
The present invention relates generally to semiconductor fabrication. More specifically, the present invention relates to material deposition and associated planarization on a semiconductor wafer.
2. Description of the Related Art
In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on semiconductor wafers. The semiconductor wafers include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
The series of manufacturing operations for defining features on the semiconductor wafers can include many processes such as adding, patterning, etching, removing, polishing, and planarizing among others, various material layers. Due to the intricate nature of the features defined on the semiconductor wafers, it is necessary to perform each process in a precise manner. For example, it is often desirable to planarize a surface of the wafer in a precise manner to decrease variations in a surface topography of the wafer. Without precise planarization, fabrication of additional metallization layers becomes substantially more difficult due to increased variations in the surface topography of the wafer.
A chemical mechanical planarization (CMP) process is one method for performing wafer planarization. In general, the CMP process involves holding and contacting a rotating wafer against a moving polishing pad under a controlled pressure. CMP systems typically configure the polishing pad on a rotary table or a linear belt. Additionally, a slurry is disposed to be present an interface between the wafer and the polishing pad to facilitate and enhance the CMP process.
While the CMP process is quite capable and useful for providing wafer planarization, there is an ever present desire to continue researching and developing alternative techniques for performing wafer planarization. In view of the foregoing, there is a need for an apparatus and a method to planarize a wafer that can be implemented either as an alternative or as a complement to the traditional CMP process.